1. Field of the Invention
This invention relates to a thin-film transistor used in liquid-crystal, display devices and a process of manufacturing the thin-film transistor.
2. Description of the Related Art
In recent years, in liquid-crystal display used as display devices such as notebook personal computers, mobile appliances and so forth, their drive systems are being changed over from simple matrix systems to active matrix systems. In particular, thin-film transistor (hereinafter often xe2x80x9cTFTxe2x80x9d) active matrix systems are becoming prevailing in which a large number of thin-film transistors have been formed on a glass substrate.
Among TFT drive systems, TFTs making use of polycrystalline silicon layers have a larger electron mobility than those making use of amorphous silicon layers. Hence, they can be fabricated on glass substrates not only as transistors of displaying pixel areas but also as driving transistors.
Conventionally, since the formation of polycrystalline silicon requires a high temperature of about 1,000xc2x0 C., it has been indispensable to use expensive quartz glass substrates as substrates. Recently, development has been brought forward on techniques by which polycrystalline silicon can be formed at a processing temperature of about 600xc2x0 C., and it has become possible to use glass materials other than quartz substrates. In this method, amorphous silicon film formed on a glass substrate is subjected to laser irradiation or the like, whereby only the amorphous silicon film can be heated and crystallized without causing a rise in substrate temperature.
Meanwhile, in integrated circuit devices making use of single-crystal silicon substrates, thermal oxides (layer thickness; about a few nm to tens of nm) of silicon are used as gate-insulating layers. However, the formation of such thermal oxide films of silicon requires heat treatment at about: 1,000xc2x0 C., and this processing can not be utilized in the process of manufacturing polycrystalline silicon TFTs which prerequisites the processing temperature of 600xc2x0 C. or below.
In processes of manufacturing TFTs, TEOS (tetraethoxysilane) is used as a material, and SiO2 layer (layer thickness: about 100 nm) formed by plasma-assisted CVD (chemical vapor deposition) is used as gate-insulating layer, The SiO2 layer formed by plasma-assisted CVD (hereinafter xe2x80x9cTEOS layerxe2x80x9d), however, has so high an interfacial state density that a great performance deterioration of TFT characteristics may be bought about as is seen in, e.g., variations of threshold voltage when it is used as the gate-insulating layer as it is. Moreover, in such a case, the breakdown strength of TFT may severely deteriorate with time to cause dielectric breakdown of the TFT as a result thereof. Accordingly, at the interface of the gate-insulating layer for TFT and the silicon layer, it is desirable to form an oxide layer having low interfacial state density, comparable to thermal oxides formed by thermal oxidation of silicon.
To cope with the above problem, e.g., Japanese Patent Application Laid-open No. 8-195494 discloses a method of manufacturing a polycrystalline silicon TFT at a processing temperature of 600xc2x0 C. or below, using a conventional highly heat-resistant glass substrate.
According to the above method disclosed in Japanese Patent Application Laid-open No. 8-195494, since the polycrystalline silicon layer is formed at a temperature of about 600xc2x0 C., a usable glass substrate is limited to what is called an annealed glass, which has previously been heat-treated. Hence, where an unannealed glass substrate is used in place of the annealed glass substrate, the temperature condition of about 600xc2x0 C. may cause a shrinkage of the glass substrate, and this may cause a warpage or strain of the glass substrate to bring about difficulties such as break of the glass substrate itself and peel of the layer in the worst.
In general, the higher strain point the glass has, the higher thermal stability it has. Such glass, however, is difficult to melt, mold and work in the step of producing the glass substrate, resulting in a high production cost. Accordingly, in order to control the cost, a production method is essential which enables use of glass which has a low strain point and is inexpensive,
Usually, alkali-free glass substrates used as substrates of thin-film transistors have a strain point of about 600xc2x0 C., and compaction (heat shrinkage) of glass becomes great abruptly as a result of heat history at a temperature a little lower than the strain point. For example, an unannealed glass substrate CORNING 7059F (trade name; available from Corning Incorporated; strain point: 593xc2x0 C.) shows a compaction of about 800 ppm as a result of heat history at 600xc2x0 C., for 1 hour and at a cooling rate of 1xc2x0 C./minute. Also, in the case of CORNING 1735F (strain point: 665xc2x0 C.), having a higher-strain point, it shows a compaction of 173 ppm upon application of the same heat history as the above, Then, it has been made possible to lower compaction due to the like heat history to about 10 ppm by carrying out annealing previously at 660xc2x0 C./1 hr.
Substrates for polycrystalline TFT panels are usually required to show a heat shrinkage rate (compaction) of 20 ppm or less. Accordingly, it has ever been considered indispensable to use annealed glass substrate. Thus, where the upper limit of processing temperature is merely lowered to the temperature of such a degree that the shrinkage of unannealed glass substrates is negligible, e.g., to 450 to 500xc2x0 C., a problem discussed below may occur.
That is, as a gate-insulating layer formed on a polycrystalline silicon layer, the SiO2 layer is commonly formed in a layer thickness of about 100 nm by plasma-assisted CVD (chemical vapor deposition) using TEOS as raw material gas. At the interface between the polycrystalline silicon layer and the insulating layer formed of TEOS, however, the TEOS layer has so high an interfacial state density that the threshold voltage required as TFT tends to vary and also the breakdown strength required as the gate-insulating layer may severely deteriorate with time. Thus, there is a great problem on the reliability of TFT.
Hence, in the case when the use of an unannealed glass substrate is premised, it is important to design to keep the upper limit of processing temperature at about 450 to 500xc2x0 C. and lower the interfacial state density between the polycrystalline silicon layer and the gate-insulating layer to a level corresponding to that of any silicon oxide layer formed by thermal oxidation.
To solve the problem discussed above, an object of the present invention is to form a highly reliable polycrystalline-silicon thin-film transistor at processing temperature that may cause no problem on the compaction even when unannealed glass substrates are used.
Here, in the present invention, a glass substrate showing a compaction of 30 ppm or higher when the glass substrate is heated at 600xc2x0 C. for 1 hour and thereafter cooled at a rate of 1xc2x0 C./minute is defined as the unannealed glass substrate.
To achieve the above object, in the present invention, i) a polysilicon crystal layer for forming a channel region, a source region and a drain region, ii) a first insulating layer and iii) a second insulating layer are formed at the upper part of an unannealed glass substrate. Also, a gate region is formed at a position corresponding to the channel region and on the second insulating layer, and a gate electrode, a source electrode and a drain electrode are also formed to make electrical interconnection with the gate region, the source region and the drain region, respectively.
Here, the first insulating layer is a silicon oxide layer formed by oxidizing the surface of a polycrystalline silicon layer doped with an element belonging to Group IIIb [e.g., boron (B)] or an element belonging to Group Vb [e.g., phosphorus (P)] of the periodic table, at its channel region at a temperature of 500xc2x0 C. or below, and is so formed as to cover the surface of at least the channel region and to be in a layer thickness of from 4 nm to 20 nm.
In the present invention, the first insulating layer silicon oxide layer is also formed by oxidizing the surface of the polycrystalline silicon layer in an atmosphere containing at least ozone.
In the present invention, the second insulating layer provided at the upper part of the first insulating layer is formed by chemical vapor deposition, physical vapor deposition or spin coating.
Since as described above the surface of the polycrystalline silicon layer doped with an element belonging to Group IIIb or an element belonging to Group Vb of the periodic table is oxidized in an ozone atmosphere, a silicon oxide layer having a larger thickness than ever can be formed, at a high rate. Also, since the surface of the polycrystalline silicon layer is oxidized, the interface between the polycrystalline silicon layer and the silicon oxide layer can be kept in a good state. Moreover, since the silicon oxide layer can be formed at a processing temperature lower than ever, a relatively inexpensive, unannealed glass substrate, which are relatively inexpensive, can be used as the substrate.
In other words, the thin-film transistor manufactured by the above method has a good interface between the surface of the channel region comprised of polycrystalline silicon and the gate-insulating layer formed thereon, and hence the thin-film transistor characteristics concerned closely with the interfacial state density thereat, as exemplified by threshold voltage, can be made to less vary, so that superior TFT characteristics can be exhibited. In addition, since the unannealed glass substrate can be used as the substrate, the TFT can be formed in a large area and yet at a low cost, compared with quartz glass substrates or the like.
Here, as a known product having a structure similar to the TFT of the present invention, Japanese Patent Application Laid-open No. 2000-164885 discloses an insulated-gate type semiconductor device, and a manufacturing process therefor, in which a gate-insulating layer containing phosphorus or boron is formed by sputtering in order to prevent Na ions from diffusing from a glass substrate. In the construction disclosed in this publication, however, a deposition process (sputtering) is used as a method of forming the gate-insulating layer, and hence hot carriers tend to be injected through the interface between the gate-insulating layer and the semiconductor to cause a deterioration with time.
Japanese Patent Application Laid-open No. 10-261801 also discloses a thin-film transistor device in which the gate-insulating layer comprises a silicon-oxide layer containing phosphorus or boron in order to prevent Na ions from diffusing from a glass substrate. However, the gate-insulating layer disclosed in this publication is formed by a deposition process (CVD), and hence the deterioration due to hot carriers injected through the interface between the gate-insulating layer and the semiconductor comes into question like the case of the foregoing Japanese Patent Application Laid-open No. 2000-164885.
In the present invention, the insulating layer formed on the channel region comprised of polycrystalline silicon is formed by a method different form the above deposition process, i.e., the SiO2 layer is formed by oxidizing the surface of a polysilicon film. Hence, a thin-film transistor can be formed which has less levels ascribable to impurities at the SiO2/p-Si interface and may cause less deterioration with time.